The present invention relates to the field of computer systems. More specifically, in one embodiment the invention provides an improved method for providing bus parity between, for example, a microprocessor and peripherals, particularly in conjunction with a bus system such as the well known Extended Industry Standard Architecture (EISA) bus.
Over the last several years a variety of bus standards have been proposed or utilized for transmission of data and address signals over a bus in a computer system. One data standard which has been widely adopted is the Extended Industry Standard Architecture or "EISA." The EISA bus standard is described in "Microprocessor Report," July 1989, which is incorporated herein by reference for all purposes. Complete descriptions of the standard are readily available from BCPR Services, Inc. of Washington, D.C.
Implementation of the EISA bus standard and similar bus standards has presented a variety of problems. For example, as bus transfer speed between a processor and a peripheral piece of equipment is increased the probability that noise or other transient effects will occur during data transmission is substantially increased. The EISA bus standard does not presently provide for data integrity checks. One possible technique for providing bus parity would be to add a dedicated bus line which would be defined as a parity valid line. However, the number of spare pins provided in the EISA bus does not allow for such a conventional parity system as only four "manufacturer specific" pins are available. A conventional parity checking technique would need five pins for parity checks: four pins for byte-wide parity and one pin for transmitting a signal indicative of whether data parity is supported.
From the above it is seen that an improved system and method for providing bus parity would be desirable, particularly in conjunction with an EISA bus.